1. Field
This disclosure relates generally to data processors, and more specifically, to providing extended addressing modes in SIMD register extensions.
2. Related Art
Increased performance in data processing systems can be achieved by allowing parallel execution of operations on multiple elements of a vector. One type of processor available today is a vector processor which utilizes vector registers for performing vector operations. However, vector processors, while allowing for higher performance, also have increased complexity and cost as compared with processors using scalar general purpose registers. That is, a vector register file within vector processors typically includes N vector registers, where each vector register includes a bank of M registers for holding M elements. Another type of known processor is a single-instruction multiple-data (SIMD) scalar processor (also referred to as a “short-vector machine”) which allows for limited vector processing while using a scalar general purpose register (GPR). Therefore, although the number of elements per operation is limited as compared to vector processors, reduced hardware is required.
Many different applications executed on SIMD processors requires specialized addressing, such as circular addressing or bit-reversed addressing. However, load and store instructions typically require a large amount of limited opcode space to encode due, for example, to large displacements. Therefore, there is often no opcode space left to support any additional functionality. Therefore, the specification of additional addressing control without increasing the opcode space is desirable.